ASIC Lab @[email protected]
None subscribers - no pronouns set
Channel focuses on teaching ASIC verification. Starting from
01:44:52
Simple UVM Testbench, from Spec to Testbench (ALU Verification with UVM)
02:35
UVM Simplified (#11 Piecing it together) (Part: 3 UVM Reporting)
10:43
UVM Simplified (#11 Piecing it together) (Part: 2 Inside the Agent)
03:05
UVM Simplified (#11 Piecing it together) (Part: 1 Stimulus)
12:24
UVM Simplified (#10 UVM Interface and Connections)
05:30
UVM Simplified (#9 UVM Sequence_item and Sequence Class)
04:04
UVM Simplified (#8 UVM Components (part 2))
05:15
UVM Simplified (#7 UVM Components (part 1))
01:35
UVM Simplified (#6 UVM Phases)
03:46
UVM Simplified (#5 UVM Env, Agent and other)
05:02
UVM Simplified (#4 UVM TEST)
03:03
UVM Simplified (#3 UVM TOP)
04:00
UVM Simplified (#2 Modules of UVM)
02:32
UVM Simplified (#1 Introduction)
X
About
Channel focuses on teaching ASIC verification. Starting from Universal Verification Methodology!
Tags